Cache coherence protocol design using VMSI (Valid Modified Shared Invalid) states
DOI:
https://doi.org/10.21928/juhd.v3n1y2017.pp274-281Keywords:
Cache coherence problem, snooping protocol, Directory-Based cache Protocols, VMSI, Cache Simulator, Shared memory, Multi processor, Dev. CAbstract
We have proposed in this research the design of a new protocol named VMSI coherence protocol in the cache in order to solve the problem of coherence which is the incompatibility of data between caches that appeared in recent multiprocessors system through the operations of reading and writing. The main purpose of this protocol is to increase processor efficiency by reducing traffic between processor and memory that have been achieved through the removal of the write back to the main memory in the case of reading or writing of shared caches because it depends on existing directory inside that cache which contains all the data that represents a subset of main memory.
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[2] EL-REWINI HESHAM & ABD-EL-BARR MOSTAFA, "ADVANCED COMPUTER ARCHITECTURE AND PARALLEL PROCESSING ", PUBLISHED BY JOHN WILEY & SONS, INC., HOBOKEN, NEW JERSEY. PUBLISHED SIMULTANEOUSLY IN CANADA, 2005, PAGES 13, 92, 114, 98.
[3] RAUBER THOMAS &R¨UNGER GUDULA, "PARALLEL PROGRAMMING FOR MULTI CORE AND CLUSTER SYSTEMS ", PUBLISHED IN THE SPRINGER HEIDELBERG DORDRECHT LONDON NEW YORK, , 2007, PAGES 31, 91.
[4] A. PATTERSON DAVID& L. HENNESSY JOHN, "COMPUTER ARCHITECTURE A QUANTITATIVE APPROACH ",MORGAN KAUFMANN IS AN IMPRINT OF ELSEVIER, 2012.
[5] HWANG KAI & A. BRIGGS FAYE, "COMPUTER ARCHITECTURE AND PARALLEL PROCESSING", COPYRIGHT BY MCGRAW-HILL, INC. IN NEW YORK ST. LOUIS SAN FRANCISCO, LONDON, PARIS, 1985.
[6] STALLING WILLIAM, "COMPUTER ORGANIZATION AND ARCHITECTURE DESIGNING FOR PERFORMANCE ", PRINTED IN THE UNITED STATES OF AMERICA BY PEARSON EDUCATION, INC., UPPER SADDLE RIVER, NEW JERSEY, 2010, 07458.
[7] MOYER BRYON, "REAL WORLD MULTI CORE EMBEDDED SYSTEMS", NEWNES IS AN IMPRINT OF ELSEVIER, UNITED STATES OF AMERICA, 2013.
[8] TIWARI ANOOP, " PERFORMANCE COMPARISON OF CACHE COHERENCE PROTOCOL ON MULTI-CORE ARCHITECTURE", DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING NATIONAL INSTITUTE OF TECHNOLOGY ROURKELA ROURKELA, ODISHA, 769008, INDIA,2014.
[9]A. PATTERSON DAVID & L. HENNESSY JOHN, "COMPUTER ORGANIZATION AND DESIGN THE HARDWARE / SOFTWARE INTERFACE ", ELSEVIER INC., 2005.
[10]AL-HOTHALI SAMAHER, SOOMRO SAFEEULLAH, ET.AL.," SNOOPY AND DIRECTORY BASED CACHE COHERENCE PROTOCOLS: A CRITICAL ANALYSIS" ,JOURNAL OF INFORMATION & COMMUNICATION TECHNOLOGY VOL. 4, NO. 1, (SPRING 2010) 01-10.
[11]G. MAYER HERBERT," MESI PROTOCOL FOR MP CACHE COHERENCE", PSU CS STATUS ,2012
[12] SAPARON AZILAH, AND BT RAZLAN FATIN NAJIHAH, " CACHE COHERENCE PROTOCOLS IN MULTI-PROCESSOR", INTERNATIONAL CONFERENCE ON COMPUTER SCIENCE AND INFORMATION SYSTEMS DUBAI (UAE), (ICSIS’2014) (ICSIS’2014),OCT 17-18, 2014
[13] HANDY JIM, "THE CACHE MEMORY BOOK – 2ND ED.", ACADEMIC PRESS SAN DIEGO NEW YORK BOSTON LONDON SYDNEY TOKYO TORONTO, 1998.
[14] JACOB BRUCE, W. NG SPENCER, T. WANG DAVID, "MEMORY SYSTEM CACHE, DRAM, DISK ",MORGAN KAUFMAN PUBLISHERS IS AN IMPRINT OF ELSEVIER, 2008.
[15] KUBIATOWICZ JOHN, "3+1 CS OF CACHING AND MANY WAYS CACHE OPTIMIZATIONS" , CS252-S07, LECTURE 15 -ELECTRICAL ENGINEERING AND COMPUTER SCIENCES UNIVERSITY OF CALIFORNIA, BERKELEY,2007.
[16] MULLINS ROBERT," CHIP MULTIPROCESSORS (ACS MPHIL)", UNIVERSITY OF CAMBRIDGE COMPUTER LABORATORY", 2011.
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Published
2017-03-31
How to Cite
Jalil, L. F., H. Al-Rawi, M. A. kareem, & Al-Nakshabandi, A. D. (2017). Cache coherence protocol design using VMSI (Valid Modified Shared Invalid) states. Journal of University of Human Development, 3(1), 274–281. https://doi.org/10.21928/juhd.v3n1y2017.pp274-281
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